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SN74LS273 Octal D Flip-Flop with Clear
The SN74LS273 is a high-speed 8-Bit Register. The register consists of eight D-Type Flip-Flops with a Common Clock and an asynchronous active LOW Master Reset. This device is supplied in a 20-pin package featuring 0.3 inch lead spacing.
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* * * *
8-Bit High Speed Register Parallel Register Common Clock and Master Reset Input Clamp Diodes Limit High-Speed Termination Effects
LOW POWER SCHOTTKY
GUARANTEED OPERATING RANGES
Symbol VCC TA IOH IOL Parameter Supply Voltage Operating Ambient Temperature Range Output Current - High Output Current - Low Min 4.75 0 Typ 5.0 25 Max 5.25 70 - 0.4 8.0 Unit V C
20
mA mA
1
PLASTIC N SUFFIX CASE 738
20 1
SOIC DW SUFFIX CASE 751D
ORDERING INFORMATION
Device SN74LS273N SN74LS273DW Package 16 Pin DIP 16 Pin Shipping 1440 Units/Box 2500/Tape & Reel
(c) Semiconductor Components Industries, LLC, 1999
1
December, 1999 - Rev. 6
Publication Order Number: SN74LS273/D
SN74LS273
CONNECTION DIAGRAM DIP (TOP VIEW)
VCC 20 Q7 19 D7 18 D6 17 Q6 16 Q5 15 D5 14 D4 13 Q4 12 CP 11
1 MR
2 Q0
3 D0
4 D1
5 Q1
6 Q2
7 D2
8 D3
9 Q3
10 GND
LOADING (Note a) PIN NAMES CP D0 - D7 MR Q0 - Q7 Clock (Active HIGH Going Edge) Input Data Inputs Master Reset (Active LOW) Input Register Outputs HIGH 0.5 U.L. 0.5 U.L. 0.5 U.L. 10 U.L. LOW 0.25 U.L. 0.25 U.L. 0.25 U.L. 5 U.L.
NOTES: a) 1 TTL Unit Load (U.L.) = 40 mA HIGH/1.6 mA LOW.
TRUTH TABLE
MR L H H CP X Dx X H L Qx L H L
H = HIGH Logic Level L = LOW Logic Level X = Immaterial
LOGIC DIAGRAM
3 11 4 7 8 13 14 17 18
D0
D1
D2
D3
D4
D5
D6
D7
CP CP D CD Q CP D CD Q CP D CD Q CP D CD Q CP D CD Q CP D CD Q CP D CD Q CP D CD Q
1
MR
VCC = PIN 20 GND = PIN 10 = PIN NUMBERS
Q0
2
Q1
5
Q2
6
Q3
9
Q4
12
Q5
15
Q6
16
Q7
19
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SN74LS273
FUNCTIONAL DESCRIPTION
The SN74LS273 is an 8-Bit Parallel Register with a common Clock and common Master Reset. When the MR input is LOW, the Q outputs are LOW, independent of the other inputs. Information meeting the
setup and hold time requirements of the D inputs is transferred to the Q outputs on the LOW-to-HIGH transition of the clock input.
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 2.7 - 0.65 3.5 0.25 VO OL Output LOW Voltage 0.35 IIH IIL IOS ICC Input HIGH Current 0.1 Input LOW Current Short Circuit Current (Note 1) Power Supply Current - 20 - 0.4 - 100 27 0.5 20 V A mA mA mA mA IOL = 8.0 mA 0.4 Min 2.0 0.8 - 1.5 Typ Max Unit V V V V V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for All Inputs VCC = MIN, IIN = - 18 mA VCC = MIN, IOH = MAX, VIN = VIH or VIL per Truth Table IOL = 4.0 mA VCC = VCC MIN, VIN = VIL or VIH per Truth Table
VCC = MAX, VIN = 2.7 V VCC = MAX, VIN = 7.0 V VCC = MAX, VIN = 0.4 V VCC = MAX VCC = MAX
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS (TA = 25C, VCC = 5.0 V)
Limits Symbol fMAX tPHL tPLH tPHL Parameter Maximum Input Clock Frequency Propagation Delay, MR to Q Output Propagation Delay, Clock to Output Min 30 Typ 40 18 17 18 27 27 27 Max Unit MHz ns ns Test Conditions Figure 1 Figure 2 Figure 1
AC SETUP REQUIREMENTS (TA = 25C, VCC = 5.0 V)
Limits Symbol tw ts th trec Parameter Pulse Width, Clock or Clear Data Setup Time Hold Time Recovery Time Min 20 20 5.0 25 Typ Max Unit ns ns ns ns Test Conditions Figure 1 Figure 1 Figure 1 Figure 2
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SN74LS273
AC WAVEFORMS
1/f max tW CP 1.3 V ts(H) D * 1.3 V tPLH Qn 1.3 V tPHL
*The shaded areas indicate when the input is permitted to *change for predictable output performance.
MR 1.3 V th(L) 1.3 V 1.3 V tPHL 1.3 V tPLH Qn CP
tW 1.3 V trec 1.3 V tPHL 1.3 V tPLH 1.3 V 1.3 V 1.3 V
1.3 V th(H)
1.3 V ts(L)
Qn
Figure 1. Clock to Output Delays, Clock Pulse Width, Frequency, Setup and Hold Times Data to Clock DEFINITION OF TERMS
Figure 2. Master Reset to Output Delay, Master Reset Pulse Width, and Master Reset Recovery Time
SETUP TIME (ts) -- is defined as the minimum time required for the correct logic level to be present at the logic input prior to the clock transition from LOW-to-HIGH in order to be recognized and transferred to the outputs. HOLD TIME (th) -- is defined as the minimum time following the clock transition from LOW-to-HIGH that the logic level must be maintained at the input in order to ensure
continued recognition. A negative HOLD TIME indicates that the correct logic level may be released prior to the clock transition from LOW-to-HIGH and still be recognized. RECOVERY TIME (trec) -- is defined as the minimum time required between the end of the reset pulse and the clock transition from LOW-to-HIGH in order to recognize and transfer HIGH data to the Q outputs.
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SN74LS273
PACKAGE DIMENSIONS
N SUFFIX PLASTIC PACKAGE CASE 738-03 ISSUE E
-A-
20 11 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. INCHES MIN MAX 1.010 1.070 0.240 0.260 0.150 0.180 0.015 0.022 0.050 BSC 0.050 0.070 0.100 BSC 0.008 0.015 0.110 0.140 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 25.66 27.17 6.10 6.60 3.81 4.57 0.39 0.55 1.27 BSC 1.27 1.77 2.54 BSC 0.21 0.38 2.80 3.55 7.62 BSC 0_ 15_ 0.51 1.01
B
1 10
C
L
-T-
SEATING PLANE
K M E G F D
20 PL
N J 0.25 (0.010)
M 20 PL
0.25 (0.010) TA
M
M
TB
M
DIM A B C D E F G J K L M N
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SN74LS273
D SUFFIX PLASTIC SOIC PACKAGE CASE 751D-05 ISSUE F
D
A
11 X 45 _
q
NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 12.65 12.95 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_
H
M
B
M
20
10X
0.25
E
1
10
h
20X
B 0.25
M
B TA
S
B
S
A
SEATING PLANE
DIM A A1 B C D E e H h L
L
18X
e
A1
q
T
C
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SN74LS273
Notes
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SN74LS273
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PUBLICATION ORDERING INFORMATION
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SN74LS273/D

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